Digital Circuit Flip Flops

The outputs of a digital circuit are dependent entirely on the input circuits. If the input changes the output also changes. However, the requirements for digital device to output remain unchanged even if there is a change in the input. Such a device could be used to store a binary number. A flip-flop is one such circuit. Thus, a flip-flop is a binary cell capable of storing one bit of information. It has two outputs, one for the normal value and other for the complement value of the bit stored in it. A flip-flop maintains a binary state until directed by a clock pulse to switch state. The difference among various types of flip-flops is in the number of inputs they possess and in the manner in which the inputs affect the binary state. The most common types of flip-flops are presented below.

SR Flip-Flop

A SR Flip-Flop has three inputs, which are labeled S (for Set), R (for Reset) and C (for Clock). The graphic symbol of the SR flip-flop is shown in the figure below. It has two outputs Q and Q’ which is the complemented output, and it is indicated with a small circle at the output terminal. The arrow-head in front of C is dynamic input which means that the flip-flop responds to a positive transition, i.e., from 0 to 1 of the input clock signal.

D Flip-Flop

The D (Data) flip-flop is a modified version of the SR flip-flop. We can convert an SR flip-flop to a D flip-flop by inserting an inverter between S and R. Then assign the symbol D to the single input. The D input is sampled during the occurrence of a clock transition from 0 to 1. If D=1, the output of the flip-flop goes to 1 state, but if D=0, the output of the flip-flop goes to the 0 state.

JK Flip-Flop

Since the output of an SR flip-flop is undefined when SR is 11, a flip-flop (JK) is designed to overcome this problem. A JK flip-flop is a refinement of the SR flip-flop in that the indeterminate condition of the SR type becomes defined in the JK type. Inputs J and K behave like inputs S and R to set and clear the flip-flop, respectively. But when inputs are J =1 and K =1, a clock transition switches the outputs of the flip-flop to their complement state.

T Flip-Flop

Another type of flip-flop is the T (Toggle) flip-flop shown below. This is obtained from a JK type when inputs J and K are connected to provide a single input designed by T. Obviously a T flip-flop has only two conditions: when T=0 (i.e. when both J and K equals to 0) a clock transition does not change the state of the flip-flop, (i.e. when both J and K equals to 0) a clock transition complements the state of the flip-flop.

Edge-triggered Flip-Flops

The flip-flops we discussed above do not change state during the change of clock pulse. In applications we need flip that change their output during the clock pulse change. The most common type of flip-flop used to synchronize the state change during a clock pulse transition is the edge-triggered flip-flop. In this type of flip-flop, output transitions occur at a specific level at the clock pulse. When the pulse input level exceeds this threshold level, the inputs are locked out so that the flip-flop is unresponsive to further changes in inputs until the clock pulse returns to 0 and another pulse occurs. Some edge-triggered flip-flops cause a transition on the rising edge of the clock signal (positive-edge transition) and others cause a transition on the falling edge (negative-edge transition).

Master Slave Flip-Flop

Second type of flip-flops that change their state during clock pulse change are master slave flip-flop, which are in some systems. This type of circuit has two flip-flops. The first is called the master, which responds to the positive level of the clock and the second is known as the slave, which responds to the negative level of the clock. The result is that the output changes during the 1 to 0 transition of the two clock signals.